In the digital satellite broadcasting, a layered transmission system is adopted in which a plurality of transmission systems with different necessary C/N (ratio of carrier level to noise level) values, for example, 8PSK, QPSK and BPSK, are combined every interval, and are transmitted repeatedly on a frame-by-frame basis.
A digital satellite broadcasting receiver to receive the digital modulated waves by such a layered transmission system enables demodulation by capturing frame synchronization signals from the demodulated base band signals, and from timings of the captured frame synchronization signals, judging the most essential information on transmission of main signals necessary to demodulate the transmitted signals, for example, a modulation system, a position of a TMCC (Transmission and Multiplexing Configuration Control) signal being a transmission multiplexing control signal for representing an error correction system and positions of burst signals.
The TMCC signals, which have undergone convolution encoding continuously, are determined in advance to be of BPSK and have an encoding ratio of the convolution encoding r=1/2. However, since a modulation system and an encoding system (an encoding ratio of convolution encoding) for TS data (hereafter referred to as a main signal or simply as TS) are not known until the TMCC signals are decoded, Viterbi Trellis decoding on the entire frame including TMCC signals and TS data becomes possible only after only TMCC signals are processed by Viterbi decoding and decoded by a TMCC decoder, and then multiplexed configuration of modulated waves, and the modulation system and encoding system for the TS data subsequent to the TMCC signal are read out.
This sort of prior art demodulator is configured as shown in FIG. 4. In FIG. 4, a demodulation circuit 1 receives as its input an intermediate frequency signal which is obtained by converting the frequency of the received digital modulated wave to a predetermined intermediate frequency and sends out base band signals I(6) and Q(6) whose number of quantized bits is 6, for example (hereinafter, they are also expressed as I and Q by omitting the number of bits. In addition, other signals are similarly expressed by omitting the number of bits).
The sent-out base band signals I and Q are inputted to a synchronization acquisition circuit 2 for acquiring the frame synchronization signals, and it will be judged that frames are synchronized when it has been confirmed that frame synchronization signals acquired in the synchronization acquisition circuit 2 are repeatedly received in every constant frame interval so that frame pulses are outputted in every frame period.
The frame pulses are inputted to a timing generation circuit 3 which creates timing signals as well as control signals necessary in circuits in a later stage to send out TMCC enable signals (hereinafter to be described also as TMCCENA), VALID signals 3-bit rate signals and selection signals (hereinafter to be also described simply as S signal) from the timing generation circuit 3.
A TMCC enable signal is a gate signal to reach a higher voltage during the period when the error-corrected TMCC signals are outputted from the Viterbi Trellis decoder 4, and during a period when the TMCC enable signals are to maintain a high voltage, the input gate of the TMCC decoder 5 opens so that the Viterbi-decoded TMCC signals are inputted to the TMCC decoder 5.
The VALID signals are signals that give rise to a lower voltage only for sections of the bust symbol signals (to be also described simply as BS signal) which arrive by transmission with a rate of 4 symbols to be inserted toward the TS data of 203 symbols for making carrier reproduction easy, and for the period while the VALID signals are kept with a lower voltage, the input gate of the Viterbi Trellis decoder 4 is closed and burst signals are removed.
S signals are signals that will be provided with a higher voltage only during the period occupied by TMCC signals. A RATE signal is a signal that has been allocated based on modulation type and encoding rate.
In addition, the TMCC decoder 5 executes predetermined decoding on the TMCC signals to return to the timing generation circuit 3 the TMCC being information such as multiplexed configuration, modulation type of TS data and encoding type, etc. The timing generation circuit 3 will be capable of generating RATE signals based on this TMCC signal.
On the other hand, the base band signal I and Q are provided to the selector 6 as well. Base band signals I, Q, and base band signals Ia and Qa which have undergone parallel conversion on the I signals as an input by an S/P converter 7 to execute serial/parallel conversion thereon are selected by S signal and outputted to the selector 6. The outputs from the selector 6 will be treated as the base band signals Ib and Qb.
The base band signals Ib and Qb are inputted to the Viterbi Trellis decoder 4 while the Viterbi Trellis 4 proceeds with decoding corresponding with the RATE signals being identification signals of modulation type as well as encoding type of the base band signals Ib and Qb in receipt thereof. The decoded data undergo serial/parallel conversion with byte as a unit from the leader of the TMCC signals so as to be outputted to TMCC decoder 5 as well as a subsequent circuit byte by byte.
S signals being selection signals of a selector 6 and RATE signals to control decoding operation of the Viterbi Trellis decoder 4 will be described with reference to FIG. 5 and FIG. 6.
An S signal is a signal to which higher voltage is given for sections under the BPSK, r=1/2 with the base band signals I and Q as shown in FIG. 5. Accordingly, the TMCC signal sections will always give higher voltages. The reason why signals under BPSK, r=1/2 always undergo serial/parallel conversion is that in a convolution encoder at the transmitting party, in case of BPSK, r=1/2, in 2-bit C0 and C1 to be outputted in parallel for a 1-bit input, parallel/serial conversion is executed with C0 as a leader to be sent out on the I axis subject to mapping, and thus it is necessary for the receiving party to proceed with decoding with opposite operation against this.
On the other hand, the RATE signals control decoding operations of the Viterbi Trellis decoder 4. As shown in FIG. 5, modulation types as well as encoding types (decoding types) are shown there. RATE=000 represents BPSK, r=1/2. In addition, RATE=001 represents QPSK, r=1/2.
However, after undergoing serial/parallel conversion as described above, BPSK, r=1/2 can be treated as QPSK, r=1/2 for Viterbi Trellis decoding, but there is difference that the rate subject to serial/parallel conversion is half compared with QPSK, r=1/2. In addition, the modulation type for RATE=010 to 101 is QPSK, but encoding rates differ in accordance with puncture encoding. In this case, depuncture decoding process corresponding with RATE, that is, an encoding rate is executed inside the Viterbi Trellis decoder 4. In addition, RATE=110 means TC (TC stands for Trellis code) 8PSK, r=2/3, and Trellis decoding is executed.
FIG. 6 describes one frame of respective signals in the prior arts shown in FIG. 4. FIG. 6(A) shows a frame pulse, which is outputted from synchronization acquisition circuit 2 in every frame interval subject to fixation of frame synchronization. FIG. 6(B) shows decoded base band signals I and Q, and exemplifies a configuration in which following the TMCC signal main signals of the TC8PSK, and the main signals of QPSK, r=1/2 are multiplexed.
FIG. 6(C) shows the S signals with higher voltage in the portion of BPSK, r=1/2. In the present example, only the TMCC section where transmission takes place under BPSK, r=1/2 is provided with a higher voltage. FIG. 6(D) shows the RATE signal with 000 for the TMCC signal section, 110 for the main signal section of TC8PSK, r=1/2, and 001 for the main signal section of QPSK, r=1/2.
However, modulation type as well as encoding type of the main signal in succession of the TMCC signal will become identifiable and controllable for the first time when the TMCC signal is decoded. Accordingly, before decoding the TMCC signals, it is necessary to execute Viterbi decoding only for the TMCC signal section.
In addition, FIGS. 6(E), 6(F) and 6(G) are timing charts respectively on the base band signals I and Q, S signal and RATE signal which have been demodulated prior to demodulation on TMCC signal. The S signal is provided with a higher voltage while the RATE signal is 000 respectively for the TMCC signal section, but unidentified otherwise.
A stream accompanied by the TMCC signals and this unidentified sections are brought into Viterbi decoding, giving rise to problems as follows. FIG. 7 is to show a technical concept of Viterbi decoding. FIG. 7(A) shows the process that 96 symbols of the TMCC signal (after serial/parallel conversion, the TMCC signal of 192 symbols will become equal to the QPSK symbol of 96 symbols) are accumulated in a pass memory and the main signal data of the subsequent TC8PSK are inputted. Currently around 96 symbols are dominant for the length of pass memory, and therefore as shown in FIG. 7(B), when the main signal is inputted, the TMCC signals are gradually decoded to be outputted.
However, in the case where modulation as well as encoding type of the main signals is unidentified, the inputted data are equal to noises, and therefore, as in FIGS. 7(C) and 7(D) noise components are gradually accumulated into the pass memory data for correcting errors to proceed with encoding, making the out-pushed TMCC signal data to become unreliable. In addition, not only the problem taking place prior to decoding of the TMCC signals but also in the case where at the time when TC8PSK is being received as a main signal, reception C/N decreases to go under C/N with which error correction remains effective for TC8PSK, the TC8PSK data are equal to noise, and thus there is a problem that reliability toward decoding on the TMCC signals decreases.
An objective of the present invention is to provide a demodulator having been improved in reliability toward decoding on TMCC signals.